As the semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs, challenges from both fabrication and design issues have resulted in the development of three dimensional designs, such as a fin-like field effect transistor (FinFET). A typical FinFET is fabricated with a thin “fin” (or fin structure) extending from a substrate, for example, etched into a silicon layer of the substrate. The channel of the FET is formed in this vertical fin. A gate is provided over (e.g., wrapping) the fin. It is beneficial to have a gate on both sides of the channel allowing gate control of the channel from both sides. Further advantages of FinFET devices include reducing the short channel effect and higher current flow.
As device structures become more dense, there have been problems associated with fabrication of FinFET devices. For example, conventional FinFET device fabrication methods utilize various implantation processes. The implantation processes may be used to form doped regions of the substrate, source and drain regions in the fin, etc. These implantation processes can induce damage (e.g., Si damage) and amorphorization effects in the substrate, fin, or other features, which can degrade device performance. As devices become smaller, Si damage and amorphorization effects cannot be easily remedied by subsequent processes, further exacerbating device performance issues. Accordingly, what is needed is a method for fabricating an IC device that addresses the above stated issues.